Xidian University team builds lightweight photonic spiking neural network for classification

A Xidian University research team says it has developed a hardware-aware photonic spiking neural network that fits chip constraints and classifies handwritten and fashion images with high accuracy. The work, published July 24, 2026 in Opto-Electronic Advances, aims to push photonic neuromorphic computing closer to practical edge deployment.

Why it matters: - The work targets a core bottleneck in photonic neural networks: the mismatch between chip hardware and algorithm size. - The approach is aimed at lower power, lower latency pattern classification for edge computing and real-time intelligent systems. - The research could help move photonic spiking neural networks from lab demonstrations toward deployable hardware.

What happened: - A team led by Prof. Xiang at Xidian University published a paper in Opto-Electronic Advances on July 24, 2026. - The paper presents a hardware-aware lightweight photonic spiking neural network for pattern classification. - The design combines frequency-domain preprocessing, custom photonic chips, and hardware-aware training.

The details: - The network uses a discrete cosine transform, or DCT, on 28×28 images to extract low-frequency features. - The DCT step reduces the input dimension from 784 to 45. - The reduced input size matches the port count of available photonic chips and lowers deployment complexity. - The team designed and fabricated a silicon-based simplified MZI mesh photonic synapse chip. - The synapse chip uses a 16×16 lightweight structure with 152 phase shifters. - The silicon chip performs low-loss, low-power linear matrix-vector multiplication in the optical domain. - The synapse chip reaches 1.39 TOPS/W energy efficiency and 0.13 TOPS/mm² computing density. - The team also built an InP-based 16-channel DFB-SA laser array photonic neuron chip. - The neuron chip implements LIF neuron nonlinear spike activation. - The neuron chip reaches a maximum self-pulsation frequency of 5.23 GHz. - The neuron chip delivers 987.65 GOPS/W energy efficiency. - The single-layer end-to-end latency is 320 ps. - The training flow has three stages: software pre-training, photonic hardware in-situ training, and hardware-aware software fine-tuning. - The team used surrogate gradient backpropagation and temporal pruning. - The method compresses inference latency to a single time step, T=1. - The training approach is designed to offset fabrication imperfections and system noise. - In software-hardware collaborative inference, the system reached 90% accuracy on MNIST. - The same setup reached 80.5% accuracy on Fashion-MNIST. - The paper says the system ranks at an international leading level among photonic neural network chips supporting optical-domain nonlinear computing. - The paper says future gains are possible through heterogeneous integration and all-optical DCT preprocessing.

Between the lines: - The main advance is not just better photonic hardware. It is the co-design of model, preprocessing, chip architecture, and training around hardware limits. - The DCT reduction is doing important practical work by shrinking the problem to fit existing chip interfaces. - The single-time-step inference focus suggests the team is prioritizing speed and energy efficiency over larger, more general software models.

What's next: - The research points toward heterogeneous integration as a path to better system performance. - All-optical DCT preprocessing is another stated direction for future improvement. - The platform is positioned for lightweight visual perception, edge computing, and embodied intelligence applications.

The bottom line: - Xidian University's system is a hardware-constrained photonic spiking neural network designed to close the gap between promising photonic algorithms and chips that can actually run them.